The present disclosure relates to integrated circuit (IC) layout design. To design an IC with some desired functionality, an IC designer uses electronic design automation (EDA) tools. These computer-based EDA tools enable the IC designer to efficiently design an electronic version of the IC, which describes in detail how a large number of semiconductor devices are to be arranged on a semiconductor substrate. These semiconductor devices, such as transistors, diodes, capacitors, resistors, and the like, can be arranged individually or in combination to form standard cells. Memory cells, logic circuits, amplifiers, inverters, and the like, are just a few examples of standard cells. Standard cells, possibly along with custom (e.g., non-standard cells) are tiled together to realize the functionality desired by the IC designer. The physical organization of the IC in this electronic design space is referred to as the layout.
To ensure that designed shapes of the layout can be properly manufactured on an actual semiconductor substrate, a number of automated verification processes are performed during EDA design. One such process is design rule checking (DRC), which determines whether the electronic version of the IC layout satisfies a series of design rules. These design rules specify certain geometric and connectivity restrictions associated with a particular semiconductor manufacturing process. The design rules ensure sufficient margins to account for variability that is expected to be encountered when the IC layout is actually manufactured in a real-world semiconductor manufacturing processes.